package miggy.cpu.instructions.bitshift;

import miggy.SystemModel;
import miggy.api.cpu.CpuFlag;
import miggy.api.cpu.DecodedInstruction;
import miggy.api.cpu.Size;
import miggy.cpu.DecodedInstructionImpl;
import miggy.cpu.operands.OperandFactory;

/*
//  Miggy - Java Amiga MachineCore
//  Copyright (c) 2008, Tony Headford
//  All rights reserved.
//
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
//  following conditions are met:
//
//    o  Redistributions of source code must retain the above copyright notice, this list of conditions and the
//       following disclaimer.
//    o  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
//       following disclaimer in the documentation and/or other materials provided with the distribution.
//    o  Neither the name of the Miggy Project nor the names of its contributors may be used to endorse or promote
//       products derived from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
//  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
//  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
//  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// $Revision: 21 $
*/
public class ROL
{
	public final int execute(int opcode, Size size)
	{
		int shift;

		if((opcode & 0x0020) == 0)
		{
			//immediate data with shift count
			shift = (opcode & 0x0e00) >> 9;
			if(shift == 0)
				shift = 8;
		}
		else
		{
			//Dn/Dn
			shift = SystemModel.CPU.getDataRegister((opcode & 0x0e00) >> 9);
		}

		int dstreg = opcode & 0x0007;
		int dstval = SystemModel.CPU.getDataRegister(dstreg);
		int odstval = dstval;
		dstval &= size.mask();

		SystemModel.CPU.clrFlag(CpuFlag.V);
		SystemModel.CPU.clrFlag(CpuFlag.C);

		if(shift > 0)
		{
			int lo = dstval >>> (size.bitSize() - shift);
			dstval <<= shift;
			dstval |= lo;
			dstval &= size.mask();

			if((dstval & 1) != 0)
			{
				SystemModel.CPU.setFlag(CpuFlag.C);
			}
		}

		if(dstval == 0)
		{
			SystemModel.CPU.setFlag(CpuFlag.Z);
		}
		else
		{
			SystemModel.CPU.clrFlag(CpuFlag.Z);
			if((dstval & size.msb()) != 0)
			{
				SystemModel.CPU.setFlag(CpuFlag.N);
			}
			else
			{
				SystemModel.CPU.clrFlag(CpuFlag.N);
			}
		}

		odstval &= ~(size.mask());
		SystemModel.CPU.setDataRegister(dstreg, odstval | dstval);
		return (size == Size.Long ? 8 : 6) + (shift << 1);
	}

	public final DecodedInstruction decode(int address, int opcode, Size size)
	{
		DecodedInstructionImpl di = new DecodedInstructionImpl("rol" + size.ext(), opcode, address, size);

		if((opcode & 0x0020) == 0)
		{
			//immediate data with shift count
			int shift = (opcode & 0x0e00) >> 9;
			if(shift == 0)
				shift = 8;

			di.setSrc(OperandFactory.literal(shift));
			di.setDst(OperandFactory.dataReg(opcode & 0x0007));
		}
		else
		{
			//Dn/Dn
			di.setSrc(OperandFactory.dataReg((opcode & 0x0e00) >> 9));
			di.setDst(OperandFactory.dataReg(opcode & 0x007));
		}

		return di;
	}
}
